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25 charge sharing model \ \ Vu) output voltage and the noise pulse are shown. The interconnect is modelled by 100 distributed LC sections for the SPICE simulation. 7V and the equivalent pulse width is 4 ns. The peak pulse height is calculated by our formula to be IV. 65V peak pulse height and pulse width equal to the input pulse width (iOns). Note that the SPICE results are consistent with a finite output resistance the noise voltage discharges before the end of the clock period. 2 I I I T N. - A.

Theorem 3 [MCWO] is NP-complete. Proof: Reduction from the travelling salesperson problem with distance matrix C(ij) and maximum Hamiltonian path cost of TC. a The proof of Theorem 3 enables the use of the heuristics developed for the travelling salesperson problem to obtain a wire ordering. Note that this NP-completeness result does not use vertical constraints as in [11] and is therefore a stronger result. Vertical constraints make channel routing NPcomplete and our result shows that crosstalk independently makes the problem intractable.

The device sizing problem includes both gate sizing and transistorsizing problems. In [9], the transistor sizing problem was formulated as a posynomial programming problem under the Elmore delay formulation for the RC tree model and solved by a sensitivity-based heuristics. Later, the authors of [13] applied the delay model developed in [10] for their transistor sizing formulation and solved it by a convex programming technique. , all transistor sizes increase or decrease by an uniform factor), or each gate has a discrete set of implementations (cells) with different driving capabilities pre-designed as a f(X) = ±.

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ACM-SIGDA Physical Design Workshop #5 1996: Proceedings by ACM-SIGDA


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